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FDF Seminar: Smash HDL bugs on the fly! (D. Radocon)
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1
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83
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25 September 2024
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Collaboration with Bell Labs on an algorithm deployment
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2
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127
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14 August 2024
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Spline interpolation in the FPGA
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1
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157
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8 August 2024
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CERN licence issue for Questasim
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1
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242
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5 August 2024
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An area for FPGA compilation installers (Vivado/Quartus)
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5
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226
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5 August 2024
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Open Source alternative to promgen.exe
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2
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98
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19 July 2024
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High speed concentration of data for interfaces with wide data word
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2
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116
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18 July 2024
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Question about HDLmake
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14
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657
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5 July 2024
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Control and Diagnostics System Generator for Complex FPGA-Based Measurement Systems
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0
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88
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2 July 2024
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DMA engine implemented with HLS
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0
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144
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2 July 2024
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UDP/TCP-IP for 1G/10G ethernet
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7
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1803
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2 July 2024
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Hog2024.2 released!
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0
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138
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1 July 2024
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32 PhD position available with INFN/INAF - deadline July 25th at 1 pm CEST
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0
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113
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27 June 2024
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Throughput Calculation
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0
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114
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21 June 2024
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FDF24 Talks' recordings on YouTube
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1
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138
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20 June 2024
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Solve this data-decoding problem in a smart combinational way
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7
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148
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19 June 2024
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ASTRON VHDL Repository
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2
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226
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19 June 2024
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Algorithm Acceleration
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2
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212
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18 June 2024
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Some material has restricted access
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4
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172
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17 June 2024
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CYNQ: Alternative to PYNQ but in C++
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1
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250
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15 June 2024
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FPGA HLS Developers Community?
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7
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238
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15 June 2024
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WebCast does not seem to work
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6
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138
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13 June 2024
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MyDDMTD and White Rabbit
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1
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183
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12 June 2024
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Wupper PCIe DMA core
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0
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240
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11 June 2024
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