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Welcome to FPGA Developers' Forum! :wave:
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0
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265
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16 May 2024
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Resources gathered in the past few years
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4
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242
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7 March 2025
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What type of pins are available?
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0
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12
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28 February 2025
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Transfer data from FPGA memory to PC interfae
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1
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36
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7 February 2025
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AXI4-Lite access from Linux issue
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3
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43
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4 February 2025
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CASPER Workshop 2025 at ASTRON
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0
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28
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29 January 2025
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JESD204C IP for ADC readout
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5
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98
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14 January 2025
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Youtube video with issues?
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0
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7
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13 January 2025
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AirHDL register map generator tool status
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3
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95
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10 January 2025
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FPGA Developers' Forum 2025
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0
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112
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7 January 2025
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2 work positions available in Cambridge, UK
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0
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65
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11 November 2024
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FDF Seminar: The FPGA design for the L0 trigger of the RICH detector of the NA62 Experiment at CERN SPS (M. Barbanera)
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0
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50
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7 November 2024
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Roadmap for future funding of the open source EDA ecosystem in Europe
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0
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39
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9 October 2024
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FDF24 Recording available
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2
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81
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8 October 2024
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FDF Seminar: Smash HDL bugs on the fly! (D. Radocon)
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1
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48
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25 September 2024
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Collaboration with Bell Labs on an algorithm deployment
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2
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70
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14 August 2024
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Spline interpolation in the FPGA
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1
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73
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8 August 2024
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CERN licence issue for Questasim
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1
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85
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5 August 2024
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An area for FPGA compilation installers (Vivado/Quartus)
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5
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86
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5 August 2024
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Open Source alternative to promgen.exe
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2
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54
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19 July 2024
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High speed concentration of data for interfaces with wide data word
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2
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78
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18 July 2024
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Question about HDLmake
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14
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292
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5 July 2024
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Control and Diagnostics System Generator for Complex FPGA-Based Measurement Systems
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2
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44
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23 July 2024
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DMA engine implemented with HLS
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2
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74
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23 July 2024
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UDP/TCP-IP for 1G/10G ethernet
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7
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537
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2 July 2024
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Hog2024.2 released!
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0
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75
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1 July 2024
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32 PhD position available with INFN/INAF - deadline July 25th at 1 pm CEST
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0
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82
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27 June 2024
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Throughput Calculation
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0
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71
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21 June 2024
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FDF24 Talks' recordings on YouTube
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1
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103
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20 June 2024
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Solve this data-decoding problem in a smart combinational way
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7
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86
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19 June 2024
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