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Welcome to FPGA Developers' Forum! :wave:
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0
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197
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16 2024
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FDF Seminar: Smash HDL bugs on the fly! (D. Radocon)
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1
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27
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25 2024
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AirHDL register map generator tool status
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0
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11
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23 2024
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Collaboration with Bell Labs on an algorithm deployment
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2
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36
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14 2024
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Spline interpolation in the FPGA
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1
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30
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8 2024
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CERN licence issue for Questasim
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1
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36
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5 2024
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An area for FPGA compilation installers (Vivado/Quartus)
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5
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40
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5 2024
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Open Source alternative to promgen.exe
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2
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32
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19 2024
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High speed concentration of data for interfaces with wide data word
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2
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63
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18 2024
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FDF24 Recording available
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0
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33
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15 2024
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Question about HDLmake
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14
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149
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5 2024
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Control and Diagnostics System Generator for Complex FPGA-Based Measurement Systems
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2
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35
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23 2024
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DMA engine implemented with HLS
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2
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44
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23 2024
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UDP/TCP-IP for 1G/10G ethernet
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7
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209
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2 2024
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Hog2024.2 released!
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0
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42
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1 2024
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32 PhD position available with INFN/INAF - deadline July 25th at 1 pm CEST
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0
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56
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27 2024
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Throughput Calculation
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0
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55
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21 2024
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FDF24 Talks' recordings on YouTube
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1
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84
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20 2024
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Solve this data-decoding problem in a smart combinational way
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7
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77
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19 2024
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ASTRON VHDL Repository
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2
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82
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19 2024
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Resources gathered in the past few years
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3
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217
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18 2024
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Algorithm Acceleration
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2
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103
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18 2024
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Some material has restricted access
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4
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121
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17 2024
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CYNQ: Alternative to PYNQ but in C++
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1
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126
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15 2024
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FPGA HLS Developers Community?
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7
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148
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15 2024
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WebCast does not seem to work
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6
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75
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13 2024
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MyDDMTD and White Rabbit
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1
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139
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12 2024
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Wupper PCIe DMA core
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0
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135
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11 2024
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