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Welcome to FPGA Developers' Forum! :wave:
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0
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301
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16 May 2024
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About the General category
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0
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40
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16 May 2024
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The Recordings of FDF25 are now public!
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0
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19
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2 June 2025
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Interested in Exploring FPGA Designs? Learn Practical Tips
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0
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11
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2 June 2025
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FDF Seminar: Innovative FPGA Customization Tools for High-Speed Data Processing in Physics Experiments (L. Colombini)
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4
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69
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26 May 2025
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Resources gathered in the past few years
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4
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274
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7 March 2025
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What type of pins are available?
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0
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29
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28 February 2025
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CASPER Workshop 2025 at ASTRON
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0
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50
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29 January 2025
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JESD204C IP for ADC readout
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5
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140
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14 January 2025
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FPGA Developers' Forum 2025
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0
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155
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7 January 2025
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2 work positions available in Cambridge, UK
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0
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77
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11 November 2024
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FDF Seminar: The FPGA design for the L0 trigger of the RICH detector of the NA62 Experiment at CERN SPS (M. Barbanera)
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0
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58
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7 November 2024
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Roadmap for future funding of the open source EDA ecosystem in Europe
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0
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46
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9 October 2024
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FDF24 Recording available
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2
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93
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8 October 2024
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FDF Seminar: Smash HDL bugs on the fly! (D. Radocon)
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1
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51
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25 September 2024
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An area for FPGA compilation installers (Vivado/Quartus)
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5
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98
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5 August 2024
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Open Source alternative to promgen.exe
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2
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61
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19 July 2024
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32 PhD position available with INFN/INAF - deadline July 25th at 1 pm CEST
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0
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88
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27 June 2024
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FDF24 Talks' recordings on YouTube
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1
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107
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20 June 2024
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Some material has restricted access
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4
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137
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17 June 2024
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CYNQ: Alternative to PYNQ but in C++
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1
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168
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15 June 2024
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FPGA HLS Developers Community?
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7
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178
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15 June 2024
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WebCast does not seem to work
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6
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87
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13 June 2024
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