UDP/TCP-IP for 1G/10G ethernet

Sharable HDL Cores
1

Hi all,

recently I am developing a DAQ system that sends data to a server using UDP packets on a 10G ethernet line.
By looking on the net for open source cores I stumbled on this library:

It seams to work well enough for my apllication, the only two issues I have at the moment are

  • it does not support “jumbo frames”
  • now my project is a mixed language project

Did anyone used this library? Do you have opinons/suggestions on other similar libraries?

If I am not mistaken someone was also planning to develop their own library maybe this can be a good staring point.

1 Like
2

Hi @nbiesuz,

Thanks for the link, the dev is also working on Corundum, which is an open source FPGA NIC.
We’re planning to add full UDP/IP modules to colibri (the tx part is already available, but not yet published), using proprietary MAC/PCS we were able to push it to 40G/100G as well.

3

Hi @alperro,
do I understand correctly you have no plan to add MAC and PHY?
is LHCb planning to have a common licence for these IPs?

Thanks,
Nicolò

4

For now, we don’t have plans to add MAC/PCS/PHY. We’re using vendors IPs of which CERN has licenses.

However, you’re welcome to add cores to colibri!

5

Hi @nbiesuz ,

I’m using this library in my project (DAQ system for the PANDA Luminosity detector, not related to CERN).

It also makes my project a mixed language one, but so far I haven’t found an open source MAC core in VHDL.
This library has worked well for me so far. I just had to make sure, to watch the tx busy flag in order to avoid buffer overflows in the transmit fifo.

1 Like
6

HI @florian,
did you implement answers to IP ping?
I was thinking about inserting this feature in my code but I never looked into it properly… do you know if there is an example I can borrow?

Thanks,
Nicolò

7

Hi,

so far I did not implement ping and I haven’t found any open core for it.
I only implemented a very simple DHCP client (things like lease time handling and renew/rebind are still missing).

Cheers,
Florian

8

Some time ago I have developed a solution for reliable Ethernet transmission from FPGA to PC - https://opencores.org/projects/fade_ether_protocol (described in https://iopscience.iop.org/article/10.1088/1748-0221/10/07/T07005).
It does not use TCP/IP to avoid latency introduced by the kernel network stack. Instead it registers its own Ethernet protocol. The solution was later on successfully extended to higher speed links (e.g. 25 Gb/s).