In 2018 our team has faced a problem of creating the control interfaces for complex FPGA-implemented digital systems. After review of existing solutions, we have created our own - “Address Generator for Wishbone”, which currently used in the DAQ firmware prepared for the CBM experiment.
The solution is described in https://doi.org/10.3390/s21217378 and is available under open source license at https://github.com/wzab/agwb. It generates the HDL implementation of the underlying control interface and access routines for control software. Arbitrary complex hierarchy of blocks and registers may be described in XML format. The whole solution is implemented in Python and may be easily extended or modified.
PS. I have reviewed commit logs in our repo, and changed 2020 to 2018. I forgot that it was started two years earlier…