JESD204C IP for ADC readout

General
1

Dear all,

for SHiP experiment in SBT subdetector we would like to setup a DAQ chain based on the TI ADC12DJ800 family, which uses serial output protocol JESD204C.

Is there an VHDL/Verilog implementation for the JESD204C RX available somewhere on the campus?

Best,

Ilja

2

Hi,

Yes, there is an IP core for JESD204C that you can request to TI via the following link:

I have the files and I can share them with you while waiting for the access from TI.
Please, send me an email in case you are interested: manoel.barros.marin@cern.ch

Cheers,

Manoel

3

Hi,

we use a TI ADC (ADS52J65), but we are using the Xilinx IP ($$$) to interface with JESD204B.

By checking the link you provided, this ADC seeems to be not supported?
I would assume the JESD204 IP should support all configuration modes?
Am I wrong?

Has anybody an experience in using this TI JESD204C IP?

Thanks,
Luca

4

Hi,

The IP core from TI is agnostic, so I believe that it should work with any FPGA.
Otherwise, you can also try the one from Analogue Devices that is open source. You can find it in their GitHub.

I tried the core from Xilinx and I did not manage to make it work, although in simulation it was working.
The IP core from TI worked very well and the implementation was straightforward.

You can use my first test project as template. You can find it though the following link (please, let me know in case you do not have access rights):

Sign in to CERN (this one has examples for several devkits and both for using with external ADC or loopback card)

I hope this helps.

Cheers,

Manoel

1 Like
5

Hi @mbarrosm, I would like to get access to your example, but I don’t have a full access to CERN.

6

Hi,

Please, contact me to manoel.barros.marin@cern.ch and I will send you the project files.

Cheers,

Manoel