hellow every one i want to initialise FPGA memory using block memory generator in ip core in vivado and then transfer this data into ¨PC with interface i used the code displayed in the image i don’t know why i can’t recieve the data in PUtty… i very aperciate your help
Hi @Samtiti_Sou, I cannot guarantee just looking at the RTL block diagram, but I see two strange things. The enable of the BRAM seems to be grounded, and the data valid signal to the UART_TX, comes from output RDY? Maybe writing a simple test bench could clarify the problem.