# Latest **URL:** https://fpga-developers-forum.web.cern.ch/latest.md [Latest](https://fpga-developers-forum.web.cern.ch/latest.md) · [Categories](https://fpga-developers-forum.web.cern.ch/categories.md) · [Tags](https://fpga-developers-forum.web.cern.ch/tags.md) --- ## [Welcome to FPGA Developers' Forum! 👋](https://fpga-developers-forum.web.cern.ch/t/welcome-to-fpga-developers-forum/5)
**Author:** [@system](https://fpga-developers-forum.web.cern.ch/u/system)\ **Replies:** 0\ **Last updated:** [16 May 2024 07:08 UTC](https://fpga-developers-forum.web.cern.ch/t/welcome-to-fpga-developers-forum/5 "2024-05-16T07:08:26Z")
We are so glad you joined us. FPGA Developers’ Forum An open place to discuss FPGA design Here are some things you can do to get started: :speaking\_head: Introduce yourself by adding information about yourself and y… --- ## [स्टोरी टीवी में 699 कट जाए तो क्या करें](https://fpga-developers-forum.web.cern.ch/t/topic/394)
**Author:** [@Soni\_Raja](https://fpga-developers-forum.web.cern.ch/u/Soni_Raja)\ **Replies:** 1\ **Last updated:** [10 November 2026 11:35 UTC](https://fpga-developers-forum.web.cern.ch/t/topic/394 "2026-11-10T11:35:45Z")
अगर आपके स्टोरी टीवी में 699 कट जाए, तो आप निम्नलिखित कदम उठा सकते हैं: सर्विस सेंटर से संपर्क 08893214863 करें: यदि समस्या बनी रहती है, तो आपको निर्माता के ग्राहक सेवा केंद्र से संपर्क 08893214863 करना चाहिए। अन्य उपक… --- ## [What's your editor/plugins/etc?](https://fpga-developers-forum.web.cern.ch/t/whats-your-editor-plugins-etc/338)
**Author:** [@fernands](https://fpga-developers-forum.web.cern.ch/u/fernands)\ **Replies:** 2\ **Last updated:** [28 April 2026 07:23 UTC](https://fpga-developers-forum.web.cern.ch/t/whats-your-editor-plugins-etc/338 "2026-04-28T07:23:33Z")
Just curious on knowing what fellow developers are using to write their code, be it VHDL, Verilog, C, C++, etc. I use Emacs in VHDL mode together with lsp-server configure to use rust\_hdl. For coding style, slowly migr… --- ## [Research Associate in Experimental Physics in Freiburg (ML on heterogeneous hardware, real-time alignment at LHCb) - applications from non-phycisits also welcome](https://fpga-developers-forum.web.cern.ch/t/research-associate-in-experimental-physics-in-freiburg-ml-on-heterogeneous-hardware-real-time-alignment-at-lhcb-applications-from-non-phycisits-also-welcome/354)
**Author:** [@mlupberg](https://fpga-developers-forum.web.cern.ch/u/mlupberg)\ **Replies:** 0\ **Last updated:** [11 November 2025 17:25 UTC](https://fpga-developers-forum.web.cern.ch/t/research-associate-in-experimental-physics-in-freiburg-ml-on-heterogeneous-hardware-real-time-alignment-at-lhcb-applications-from-non-phycisits-also-welcome/354 "2025-11-11T17:25:16Z")
Dear colleagues, there is a new research consortium in Germany working on ML algorithms and tools for transferring ML models to Versal AI and SiM AI devices. Find more information here: https://www.erumdata-deep.de/ Tw… --- ## [How does it maintain output stability?](https://fpga-developers-forum.web.cern.ch/t/how-does-it-maintain-output-stability/353)
**Author:** [@Luosi](https://fpga-developers-forum.web.cern.ch/u/Luosi)\ **Replies:** 0\ **Last updated:** [4 November 2025 07:45 UTC](https://fpga-developers-forum.web.cern.ch/t/how-does-it-maintain-output-stability/353 "2025-11-04T07:45:22Z")
How does the EN5322QI maintain output stability with minimal external components? --- ## [PCIe Gen6 Controller IP: Powering the Next Wave of High-Speed Data Applications](https://fpga-developers-forum.web.cern.ch/t/pcie-gen6-controller-ip-powering-the-next-wave-of-high-speed-data-applications/352)
**Author:** [@Ayushi\_Chaurasia](https://fpga-developers-forum.web.cern.ch/u/Ayushi_Chaurasia)\ **Replies:** 0\ **Last updated:** [24 September 2025 10:24 UTC](https://fpga-developers-forum.web.cern.ch/t/pcie-gen6-controller-ip-powering-the-next-wave-of-high-speed-data-applications/352 "2025-09-24T10:24:30Z")
The demand for faster, more reliable, and scalable interconnects is higher than ever. From data-hungry AI/ML workloads to high-performance computing (HPC) and data centers, the backbone of modern innovation lies in how q… --- ## [FDF Seminar: GateMate: A European 28nm FPGA with an Open-Source Toolchain and Radiation Qualification Results (P. Urban)](https://fpga-developers-forum.web.cern.ch/t/fdf-seminar-gatemate-a-european-28nm-fpga-with-an-open-source-toolchain-and-radiation-qualification-results-p-urban/351)
**Author:** [@rzou1](https://fpga-developers-forum.web.cern.ch/u/rzou1)\ **Replies:** 0\ **Last updated:** [23 September 2025 12:58 UTC](https://fpga-developers-forum.web.cern.ch/t/fdf-seminar-gatemate-a-european-28nm-fpga-with-an-open-source-toolchain-and-radiation-qualification-results-p-urban/351 "2025-09-23T12:58:46Z")
Dear FDF community, The next FPGA Developers’ Forum Seminar will take place TODAY, Sep 23rd, at 16.00 CET on ZOOM only. Patrick Urban (Cologne Chip) will present: GateMate: A European 28nm FPGA with an Open-Source T… --- ## [Is it suitable for space design?](https://fpga-developers-forum.web.cern.ch/t/is-it-suitable-for-space-design/348)
**Author:** [@Luosi](https://fpga-developers-forum.web.cern.ch/u/Luosi)\ **Replies:** 0\ **Last updated:** [17 September 2025 03:19 UTC](https://fpga-developers-forum.web.cern.ch/t/is-it-suitable-for-space-design/348 "2025-09-17T03:19:47Z")
What makes the NVMFD5C674NLT1G suitable for space-constrained designs? --- ## [Hog for Vivado (HDL) and Vitis (Software - bare-metal)](https://fpga-developers-forum.web.cern.ch/t/hog-for-vivado-hdl-and-vitis-software-bare-metal/341)
**Author:** [@Dominik](https://fpga-developers-forum.web.cern.ch/u/Dominik)\ **Replies:** 0\ **Last updated:** [7 August 2025 13:59 UTC](https://fpga-developers-forum.web.cern.ch/t/hog-for-vivado-hdl-and-vitis-software-bare-metal/341 "2025-08-07T13:59:34Z")
Hi there, I’m working on a Vivado project with a Zynq processor and using Hog for the HDL portion. I’m wondering about the best way to handle the associated software project. Does Hog have any built-in support for mana… --- ## [Reputability & Awareness - Bliss Paradox](https://fpga-developers-forum.web.cern.ch/t/reputability-awareness-bliss-paradox/337)
**Author:** [@Beverly\_Nicole](https://fpga-developers-forum.web.cern.ch/u/Beverly_Nicole)\ **Replies:** 0\ **Last updated:** [13 July 2025 07:18 UTC](https://fpga-developers-forum.web.cern.ch/t/reputability-awareness-bliss-paradox/337 "2025-07-13T07:18:03Z")
My whole perspective changed about online marketing and investment after my liberation from a traumatic experience in digital marketing. --- ## [Lattice MACHXO3LF-6900C](https://fpga-developers-forum.web.cern.ch/t/lattice-machxo3lf-6900c/334)
**Author:** [@Matis\_Richet](https://fpga-developers-forum.web.cern.ch/u/Matis_Richet)\ **Replies:** 0\ **Last updated:** [3 July 2025 09:30 UTC](https://fpga-developers-forum.web.cern.ch/t/lattice-machxo3lf-6900c/334 "2025-07-03T09:30:18Z")
I am working on a project to emulate a 1980s AM2764-A prom on an FPGA component (MACHXO3LF-6900C). I have created a project that works in simulation. However, when it comes to implementing it on the board, I am unable to… --- ## [Does it support high-speed serial transceivers?](https://fpga-developers-forum.web.cern.ch/t/does-it-support-high-speed-serial-transceivers/329)
**Author:** [@Luosi](https://fpga-developers-forum.web.cern.ch/u/Luosi)\ **Replies:** 1\ **Last updated:** [24 June 2025 08:48 UTC](https://fpga-developers-forum.web.cern.ch/t/does-it-support-high-speed-serial-transceivers/329 "2025-06-24T08:48:27Z")
Does the 5CGXFC5C6F23I7N support high-speed serial transceivers? --- ## [AXI4-Lite access from Linux issue](https://fpga-developers-forum.web.cern.ch/t/axi4-lite-access-from-linux-issue/225)
**Author:** [@lukipedio](https://fpga-developers-forum.web.cern.ch/u/lukipedio)\ **Replies:** 5\ **Last updated:** [9 June 2025 12:19 UTC](https://fpga-developers-forum.web.cern.ch/t/axi4-lite-access-from-linux-issue/225 "2025-06-09T12:19:49Z")
I am facing an issue that maybe someone of you has already encountered a possible fixed. Let me start by saying that this is a software issue basically, but it is related to FPGA developing since I am facing this on a X… --- ## [FPGA Developers' Forum 2025](https://fpga-developers-forum.web.cern.ch/t/fpga-developers-forum-2025/221)
**Author:** [@dcieri](https://fpga-developers-forum.web.cern.ch/u/dcieri)\ **Replies:** 1\ **Last updated:** [9 June 2025 05:34 UTC](https://fpga-developers-forum.web.cern.ch/t/fpga-developers-forum-2025/221 "2025-06-09T05:34:48Z")
Happy new year, everybody! There are still three weeks left to submit your abstract for the 2nd FPGA Developers’ Forum (FDF25) meeting, happening at CERN, from 20th to 23rd May 2025. To submit your abstract or for more … --- ## [JESD204C IP for ADC readout](https://fpga-developers-forum.web.cern.ch/t/jesd204c-ip-for-adc-readout/203)
**Author:** [@ibekman](https://fpga-developers-forum.web.cern.ch/u/ibekman)\ **Replies:** 6\ **Last updated:** [8 June 2025 17:35 UTC](https://fpga-developers-forum.web.cern.ch/t/jesd204c-ip-for-adc-readout/203 "2025-06-08T17:35:00Z")
Dear all, for SHiP experiment in SBT subdetector we would like to setup a DAQ chain based on the TI ADC12DJ800 family, which uses serial output protocol JESD204C. Is there an VHDL/Verilog implementation for the JESD204… --- ## [The Recordings of FDF25 are now public!](https://fpga-developers-forum.web.cern.ch/t/the-recordings-of-fdf25-are-now-public/320)
**Author:** [@dcieri](https://fpga-developers-forum.web.cern.ch/u/dcieri)\ **Replies:** 0\ **Last updated:** [2 June 2025 17:54 UTC](https://fpga-developers-forum.web.cern.ch/t/the-recordings-of-fdf25-are-now-public/320 "2025-06-02T17:54:22Z")
Watch all the presentations on our youtube channel: https://www.youtube.com/playlist?list=PLMvfX5C2G0PDNjys0U6QtCTXQ1xtaWp70 --- ## [Interested in Exploring FPGA Designs? Learn Practical Tips](https://fpga-developers-forum.web.cern.ch/t/interested-in-exploring-fpga-designs-learn-practical-tips/319)
**Author:** [@Patrick\_Hopper](https://fpga-developers-forum.web.cern.ch/u/Patrick_Hopper)\ **Replies:** 0\ **Last updated:** [2 June 2025 17:33 UTC](https://fpga-developers-forum.web.cern.ch/t/interested-in-exploring-fpga-designs-learn-practical-tips/319 "2025-06-02T17:33:50Z")
Whether you’re new to FPGAs or an experienced designer, this webinar will help broaden your understanding of FPGA design considerations with hands-on knowledge with Altera, Terasic and iWave. Learn more: https://resourc… --- ## [FDF Seminar: Innovative FPGA Customization Tools for High-Speed Data Processing in Physics Experiments (L. Colombini)](https://fpga-developers-forum.web.cern.ch/t/fdf-seminar-innovative-fpga-customization-tools-for-high-speed-data-processing-in-physics-experiments-l-colombini/280)
**Author:** [@rzou1](https://fpga-developers-forum.web.cern.ch/u/rzou1)\ **Replies:** 4\ **Last updated:** [26 May 2025 14:42 UTC](https://fpga-developers-forum.web.cern.ch/t/fdf-seminar-innovative-fpga-customization-tools-for-high-speed-data-processing-in-physics-experiments-l-colombini/280 "2025-05-26T14:42:47Z")
Dear FDF community, In the next FDF seminar, we will have a presentation from Andrea Abba (Nuclear Instruments) and Luca Colombini (CAEN) on the following topic: Innovative FPGA Customization Tools for High-Speed Data … --- ## [Preferred streaming interface](https://fpga-developers-forum.web.cern.ch/t/preferred-streaming-interface/278)
**Author:** [@matthewd](https://fpga-developers-forum.web.cern.ch/u/matthewd)\ **Replies:** 1\ **Last updated:** [3 April 2025 13:50 UTC](https://fpga-developers-forum.web.cern.ch/t/preferred-streaming-interface/278 "2025-04-03T13:50:36Z")
Hi all, I’m working on a project that requires some custom DSP cores that will send and receive data streams. I know that the preferred interface for open source cores is Wishbone, but there is currently no wishbone str… --- ## [Resources gathered in the past few years](https://fpga-developers-forum.web.cern.ch/t/resources-gathered-in-the-past-few-years/104)
**Author:** [@andreas.vgenopoulos](https://fpga-developers-forum.web.cern.ch/u/andreas.vgenopoulos)\ **Replies:** 4\ **Last updated:** [7 March 2025 15:10 UTC](https://fpga-developers-forum.web.cern.ch/t/resources-gathered-in-the-past-few-years/104 "2025-03-07T15:10:28Z")
This channel has some resources gathered, that are related (almost completely) to all aspects of FPGA devices, with input from CERN people. Also sometimes there have been specific issue discussions. It is generic, most s… --- ## [What type of pins are available?](https://fpga-developers-forum.web.cern.ch/t/what-type-of-pins-are-available/269)
**Author:** [@Luosi](https://fpga-developers-forum.web.cern.ch/u/Luosi)\ **Replies:** 0\ **Last updated:** [28 February 2025 11:30 UTC](https://fpga-developers-forum.web.cern.ch/t/what-type-of-pins-are-available/269 "2025-02-28T11:30:02Z")
What type of I/O pins are available on the 10M08SCE144I7G? --- ## [Transfer data from FPGA memory to PC interfae](https://fpga-developers-forum.web.cern.ch/t/transfer-data-from-fpga-memory-to-pc-interfae/258)
**Author:** [@Samtiti\_Sou](https://fpga-developers-forum.web.cern.ch/u/Samtiti_Sou)\ **Replies:** 1\ **Last updated:** [7 February 2025 08:00 UTC](https://fpga-developers-forum.web.cern.ch/t/transfer-data-from-fpga-memory-to-pc-interfae/258 "2025-02-07T08:00:30Z")
hellow every one i want to initialise FPGA memory using block memory generator in ip core in vivado and then transfer this data into ¨PC with interface i used the code displayed in the image i don’t know why i can’t rec… --- ## [CASPER Workshop 2025 at ASTRON](https://fpga-developers-forum.web.cern.ch/t/casper-workshop-2025-at-astron/244)
**Author:** [@daniel\_astron](https://fpga-developers-forum.web.cern.ch/u/daniel_astron)\ **Replies:** 0\ **Last updated:** [29 January 2025 13:56 UTC](https://fpga-developers-forum.web.cern.ch/t/casper-workshop-2025-at-astron/244 "2025-01-29T13:56:28Z")
FYI, the CASPER Workshop 2025 will be hosted by ASTRON on Sep 8…12 in Dwingeloo, Netherlands. CASPER Workshop 2025 | ASTRON The CASPER workshop is a semi-annual workshop where FPGA, GPU, and general heterogeneous syste… --- ## [Youtube video with issues?](https://fpga-developers-forum.web.cern.ch/t/youtube-video-with-issues/239)
**Author:** [@lukipedio](https://fpga-developers-forum.web.cern.ch/u/lukipedio)\ **Replies:** 0\ **Last updated:** [13 January 2025 07:49 UTC](https://fpga-developers-forum.web.cern.ch/t/youtube-video-with-issues/239 "2025-01-13T07:49:39Z")
I was trying to view again the HLS4ML presentation on Youtube, but in my case the video stop working after a while. Does anyone else have seen this behaviour? Luca --- ## [AirHDL register map generator tool status](https://fpga-developers-forum.web.cern.ch/t/airhdl-register-map-generator-tool-status/180)
**Author:** [@naranzab](https://fpga-developers-forum.web.cern.ch/u/naranzab)\ **Replies:** 3\ **Last updated:** [10 January 2025 09:20 UTC](https://fpga-developers-forum.web.cern.ch/t/airhdl-register-map-generator-tool-status/180 "2025-01-10T09:20:26Z")
Dear all, I am currently working at the Electronics Unit at the European Synchrotron in Grenoble (France), and we decided to use AirHDL register generator tool for new projects. However, we recently learned the heartbre… --- ## [2 work positions available in Cambridge, UK](https://fpga-developers-forum.web.cern.ch/t/2-work-positions-available-in-cambridge-uk/192)
**Author:** [@reza](https://fpga-developers-forum.web.cern.ch/u/reza)\ **Replies:** 0\ **Last updated:** [11 November 2024 16:37 UTC](https://fpga-developers-forum.web.cern.ch/t/2-work-positions-available-in-cambridge-uk/192 "2024-11-11T16:37:00Z")
If anyone is interested in these opportunities, please feel free to drop me a message. The workplace is flexible and you can work remotely if you prefer to: Job Title: FPGA Engineer – High-Performance Computing Accelerat… --- ## [FDF Seminar: The FPGA design for the L0 trigger of the RICH detector of the NA62 Experiment at CERN SPS (M. Barbanera)](https://fpga-developers-forum.web.cern.ch/t/fdf-seminar-the-fpga-design-for-the-l0-trigger-of-the-rich-detector-of-the-na62-experiment-at-cern-sps-m-barbanera/189)
**Author:** [@dcieri](https://fpga-developers-forum.web.cern.ch/u/dcieri)\ **Replies:** 0\ **Last updated:** [7 November 2024 08:33 UTC](https://fpga-developers-forum.web.cern.ch/t/fdf-seminar-the-fpga-design-for-the-l0-trigger-of-the-rich-detector-of-the-na62-experiment-at-cern-sps-m-barbanera/189 "2024-11-07T08:33:25Z")
Dear FDF community, We are pleased to announce that the first FDF seminar will take place on November 26th, 2024, at 4:00 PM CET. Mattia Barbanera from University and INFN Perugia, Italy will be giving a talk titled: … --- ## [Roadmap for future funding of the open source EDA ecosystem in Europe](https://fpga-developers-forum.web.cern.ch/t/roadmap-for-future-funding-of-the-open-source-eda-ecosystem-in-europe/186)
**Author:** [@serrano](https://fpga-developers-forum.web.cern.ch/u/serrano)\ **Replies:** 0\ **Last updated:** [9 October 2024 13:54 UTC](https://fpga-developers-forum.web.cern.ch/t/roadmap-for-future-funding-of-the-open-source-eda-ecosystem-in-europe/186 "2024-10-09T13:54:08Z")
Dear all, Sorry if you get this more than once. I am posting to several channels and forums. The FOSSi Foundation is contributing to a community-wide effort to provide European policy makers with an actionable roadmap f… --- ## [FDF24 Recording available](https://fpga-developers-forum.web.cern.ch/t/fdf24-recording-available/148)
**Author:** [@dcieri](https://fpga-developers-forum.web.cern.ch/u/dcieri)\ **Replies:** 2\ **Last updated:** [8 October 2024 11:41 UTC](https://fpga-developers-forum.web.cern.ch/t/fdf24-recording-available/148 "2024-10-08T11:41:21Z")
The recording of the first FPGA Developers’ Forum are finally available. You can (re-)watch your favourite talks, on YouTube or on the CERN CDS archive. --- ## [FDF Seminar: Smash HDL bugs on the fly! (D. Radocon)](https://fpga-developers-forum.web.cern.ch/t/fdf-seminar-smash-hdl-bugs-on-the-fly-d-radocon/181)
**Author:** [@dcieri](https://fpga-developers-forum.web.cern.ch/u/dcieri)\ **Replies:** 1\ **Last updated:** [25 September 2024 10:20 UTC](https://fpga-developers-forum.web.cern.ch/t/fdf-seminar-smash-hdl-bugs-on-the-fly-d-radocon/181 "2024-09-25T10:20:07Z")
We are pleased to announce that the first FDF seminar will take place on September 24th, 2024, at 4:00 PM CET. David Racodon, CTO at Linty Services, will be giving a talk titled: “Smash HDL Bugs on the Fly!” . Here’… [Next page](https://fpga-developers-forum.web.cern.ch/latest.md?page=1)