# Sharable HDL Cores

**URL:** https://fpga-developers-forum.web.cern.ch/c/sharable-hdl-cores/5.md

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## [About the Sharable HDL Cores category](https://fpga-developers-forum.web.cern.ch/t/about-the-sharable-hdl-cores-category/14)

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**Author:** [@dcieri](https://fpga-developers-forum.web.cern.ch/u/dcieri)\
**Replies:** 0\
**Last updated:** [6 June 2024 07:55 UTC](https://fpga-developers-forum.web.cern.ch/t/about-the-sharable-hdl-cores-category/14 "2024-06-06T07:55:43Z")

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A place to discuss HDL modules that are shared under any licence to be used in any FPGA design.

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## [Preferred streaming interface](https://fpga-developers-forum.web.cern.ch/t/preferred-streaming-interface/278)

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**Author:** [@matthewd](https://fpga-developers-forum.web.cern.ch/u/matthewd)\
**Replies:** 1\
**Last updated:** [3 April 2025 13:50 UTC](https://fpga-developers-forum.web.cern.ch/t/preferred-streaming-interface/278 "2025-04-03T13:50:36Z")

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Hi all, I’m working on a project that requires some custom DSP cores that will send and receive data streams. I know that the preferred interface for open source cores is Wishbone, but there is currently no wishbone str…

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## [UDP/TCP-IP for 1G/10G ethernet](https://fpga-developers-forum.web.cern.ch/t/udp-tcp-ip-for-1g-10g-ethernet/89)

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**Author:** [@nbiesuz](https://fpga-developers-forum.web.cern.ch/u/nbiesuz)\
**Replies:** 7\
**Last updated:** [2 July 2024 13:05 UTC](https://fpga-developers-forum.web.cern.ch/t/udp-tcp-ip-for-1g-10g-ethernet/89 "2024-07-02T13:05:29Z")

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Hi all, recently I am developing a DAQ system that sends data to a server using UDP packets on a 10G ethernet line. By looking on the net for open source cores I stumbled on this library: It seams to work well enoug…

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## [ASTRON VHDL Repository](https://fpga-developers-forum.web.cern.ch/t/astron-vhdl-repository/125)

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**Author:** [@daniel\_astron](https://fpga-developers-forum.web.cern.ch/u/daniel_astron)\
**Replies:** 2\
**Last updated:** [19 June 2024 07:20 UTC](https://fpga-developers-forum.web.cern.ch/t/astron-vhdl-repository/125 "2024-06-19T07:20:54Z")

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Hi all, I just wanted to share a link to our (ASTRON / RealTime System Development) VHDL Git repo: RTSD / HDL · GitLab (astron.nl) The above is our current and maintained repo with layered libraries of VHDL modules wit…

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## [Wupper PCIe DMA core](https://fpga-developers-forum.web.cern.ch/t/wupper-pcie-dma-core/47)

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**Author:** [@fschreud](https://fpga-developers-forum.web.cern.ch/u/fschreud)\
**Replies:** 0\
**Last updated:** [11 June 2024 12:10 UTC](https://fpga-developers-forum.web.cern.ch/t/wupper-pcie-dma-core/47 "2024-06-11T12:10:22Z")

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Hello all, I would like to promote Wupper, an open source PCIe DMA core for Xilinx FPGAs including Virtex7, Kintex Ultrascale, Virtex Ultrascale+, Versal Prime and Versal Premium. https://opencores.org/projects/virtex7…